Arithmetic Compactors Design: Application to Mixed Signal Systems

Year: 2012

Issue: Feb-Apr   

Title: Arithmetic Compactors Design: Application to Mixed Signal Systems 

Author Name: Vadim Geurkov, Lev Kirischian 

Synopsis: 

Arithmetic error-control codes have been used to protect data transmission and processing. These codes are implemented through the use of appropriate encoding/decoding devices. An important part of these devices is a residue computing circuit, which has also found its application in mixed-signal systems testing. Arithmetic error-control codes originated to protect data transfers over binary channels; therefore the design methodology for residue computing circuits has been mostly oriented to the binary case. A non-binary design technique has only been known for the special type of compaction modulo. In this work, we consider a design technique for a multiple-bit arithmetic compaction circuit with an arbitrary compaction modulus. The compaction process causes some errors in the data being compacted to escape from detection. It is assumed that these data are distorted (the rate of distortion is known), which additionally increases the error escape rate. We show how to design compaction circuits that do not increase the error escape rate due to distortion.