Vol. 2 No.1
Year: 2013
Issue:
Feb-Apr
Title : Clock
Pair Shared Pulsed Flipflop
Author Name : P. Hemanth Kumar, G
Rajesh
Synopsis:
Low power flip-flops which
play a vital role for the design of low-power digital systems. Flip flops and
latches consume large amount of power due to redundant transitions and clocking
system. In addition, the energy consumed by low skew clock distribution network
is steadily increasing and becoming a larger fraction of the chip power.
Almost, 30% -60% of total power dissipation in a system is due to flip flops
and clock distribution network. In order to achieve a design that is both high
performances while also being power efficient, careful attention must be paid
to the design of flip flops and latches. The authors survey a set of flip flops
designed for low power and High performance.
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