Conventional CMOS Full-Adder for Energy-Efficient Arithmetic Applications Using SR-CPL and DPL

Vol. 4  Issue 4
Year:2016
Issue:Nov-Jan
Title:Conventional CMOS Full-Adder for Energy-Efficient Arithmetic Applications Using SR-CPL and DPL
Author Name:Jayampu Manohar, P. Hari Krishna and K.V. Ramanaiah
Synopsis:
Energy-efficiency is one of the most required features of modern electronic systems designed for high-performance and/or portable applications. Now-a-days the need for having greater computing power based on battery operated mobile devices is increasing. For this, instead of optimizing the conventional delay time and area size, it is also required to minimize the power dissipation while still maintaining the high performance. An adder is an important element of all the arithmetic and logic units. The recent trends in VLSI are moving towards the need of the devices, which consume low power. Binary adders are one of the most basic and widely used in arithmetic operations. Full-adder is the fundamental unit to carry out the addition. Numerous logics have been proposed in the literature to implement full adder using MOS transistors, namely Pass transistor logic, Double pass transistor logic, DVL, CPL, etc. Full-adder implementing with a DPL logic style uses XOR/XNOR gates, and a pass-transistor based multiplexer to obtain the Sum (So) output, and SR-CPL logic style uses only XOR/XNOR gates. In both cases, the AND/OR gates are build using a powerless and groundless pass-transistor configuration, respectively, and pass-transistor based multiplexer to get the Carry (Co ) output. In this paper, DPL (Proposed Method), and SR-CPL are implemented using PSPICE software, among them SR-CPL shows better performance in Power Dissipation and it occupies less area in IC.