Analyzing the Threshold Voltage and Subthreshold Slope of Bulk and SOI MOSFET in Silvaco

Volume 5 Issue 4 January - June 2017

Research Paper

Analyzing the Threshold Voltage and Subthreshold Slope of Bulk and SOI MOSFET in Silvaco

Nitin Sachdeva* , Pooja**, Alka***

* Research Scholar, Department of VLSI Design, YMCA UST, Faridabad, India.

**-*** Postgraduate, Department of VLSI Design, YMCA UST, Faridabad, India.

Sachdeva,N., Pooja., Alka. (2017). Analyzing the Threshold Voltage and Subthreshold Slope of Bulk and SOI MOSFET in Silvaco. i-manager’s Journal on Embedded Systems, 5(4), 11-16. https://doi.org/10.26634/jes.5.4.13600

Abstract

Currently, the expansion of VLSI industry is primarily focussed on the way to the efficiency of semiconductor devices which in turn is extremely dependent on the advancement in the CMOS technology. As the scaling down of device dimensions are being aggressive, gate tunnelling effect, p-n junction leakage current increases, and sub-threshold slope increases. More precise and novel device structures are required to be developed for overcoming the above mentioned problems. These needs have led to the development of alternative technology. So SOI technology has been invented with a buried oxide layer in the silicon substrate. Due to the isolation created by this buried oxide in the substrate, various short channel effects have been reduced. This paper presents an electrical comparison between a 45 nm n-channel Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) and 45 nm Silicon On Insulator (SOI) MOSFET simulated using SILVACO ATLAS simulator. The fabrication of both the devices have been carried out in SILVACO TCAD software and estimation of threshold voltage, drain current, and sub-threshold slope has been done. Drain current versus gate voltage and drain current versus drain voltage curves have been plotted and compared. By comparing the characteristics of the bulk and SOI MOSFET, the SOI MOSFET has been found to be better than the bulk NMOSFET.