Adaptive Compensation Techniques For Power Consumption Of Sub-Threshold Circuits – A Review

Year: 2012

Issue: Feb-Apr   

Title: Adaptive Compensation Techniques For Power Consumption Of Sub-Threshold Circuits – A Review 

Author Name: Jasmer Singh, K .Saha , G. L. Pahuja 

Synopsis: 

IC Designers are struggling for tradeoff between significant variation effects and very tight power constraints in current nanometer regime. Usage of conventional timing safety margin approach becomes the cause of continuous power consumption to prevent the design from low probability timing variations.  Various solutions have been proposed to achieve optimized power consumption/dissipation. Dynamic Threshold Voltage Vth Scaling (DVTS), Dynamic Voltage Scaling (DVS) and Dynamic Voltage and Frequency Scaling (DVFS) are some of the reported techniques in literature to achieve optimized power consumption. These approaches deals with aggressive standby Vth and VDD scaling by tracking PVT variations to smartly tradeoff between safety of data and decreased power consumption. In this paper different power saving strategies are discussed along with their benefits and limitations. This study will be helpful to select an effective power saving strategy to minimize the power dissipation.