2-Bit Ex-Or Link Based Reversible Multiplier For Low Power DSP Applications

Vol. 3  Issue 1
Year:2014
Issue:Feb-Apr
Title:2-Bit Ex-Or Link Based Reversible Multiplier For Low Power DSP Applications
Author Name:Bharathi and Neelima Koppala 
Synopsis:
The multiplier in any arithmetic unit dissipates a significant amount of energy as large number of computations are required if the number of bits in the design increase. Thus, if efficient reversible logic is used, then the power consumption can be reduced drastically as the information bits are not lost in case of reversible computation. This Paper focuses on the design of two-bit multiplier using a synthesis approach called Exorlink which reduces quantum cost compared to the technique Disjoint Sum of Products (DSOP). The design is coded in VHDL, simulated using ISIM and synthesized using Xilinx ISE 10.1i for the device Spartan3E FPGA.