Classification and Evaluation of Transition Reduction Data Encoding Techniques for Low Power SOC/NOC Interconnects

Volume 6 Issue 1 July - December 2017

Review Paper

Classification and Evaluation of Transition Reduction Data Encoding Techniques for Low Power SOC/NOC Interconnects

N. Chintaiah* , G. Umamaheswara Reddy**

* Research Scholar, Department of Electronics and Communication Engineering, Sri Venkateswara University College of Engineering, Sri Venkateswara University, Tirupati, India.

** Professor, Department of Electronics and Communication Engineering, Sri Venkateswara University College of Engineering, Sri Venkateswara University, Tirupati, India.

Chintaiah, N., and Reddy, U, G. (2017). Classification and Evaluation of Transition Reduction Data Encoding Techniques for Low Power SOC/NOC Interconnects. i-manager's Journal on Embedded Systems, 6(1), 35-46. https://doi.org/10.26634/jes.6.1.13895

Abstract

Signal integrity is becoming more and more challenging as technology changes scales down in the direction of Deep Sub Micron (DSM) technology. Interconnects are now considered the bottleneck in the design of Integrated Circuits. In the DSM technology, a coupling capacitance between interconnects is the dominant factor in the total wire capacitance. The coupling effect (capacitance formation) dominates the consumption of energy in the run-instant on the chip bus. The present survey paper with an object is to provide an overview of various approaches of encoding to reduce the coupling capacitance effect for focusing on the coding scheme to reduce switching activities on the bus. These encoding techniques are mainly memory based, degree of encoding adaptability, the amount of extra information needed for coding the targeted capacitance for switching reduction and the method for the implementation of encoding.