Design and Implementation of Combinational Circuits using Signal Distribution Network for Quantum Dot Cellular Automata

Volume 7 Issue 2 January - June 2019

Research Paper

Design and Implementation of Combinational Circuits using Signal Distribution Network for Quantum Dot Cellular Automata

R. Gurunadha*

*Department of Electronics and Communication Engineering, JNTUK University, Vizianagaram, Andhra Pradesh, India.

Gurunadha, R. (2019). Design and Implementation of Combinational Circuits using Signal Distribution Network for Quantum Dot Cellular Automata. i-manager's Journal on Embedded Systems, 7(2), 41-47. https://doi.org/10.26634/jes.7.2.16316

Abstract

Among the emerging technologies recently proposed as alternatives to the classic CMOS, Quantum-dot cellular automata (QCA) is one of the most promising solutions to design ultra-low power and very high speed digital circuits. Efficient QCA-based implementations have been demonstrated for several binary and decimal arithmetic circuits, but significant improvements are still possible if the logic gates inherently available within the QCA technology are smartly exploited. Signal Distribution Network (SDN) is one of the effective methods for the design of combinational and sequential circuits in quantum dot cellular automata. It overcomes the fabrication errors and thermal effects which occurred in wire crossings. The main objective is to increase the speed of digital circuits in QCA with the help of SDN. The main goal of this work is to reduce the hardware requirements of the digital logic circuits by using majority gate logic. The cell count and area can be reduced by logic synthesis. The main feature of SDN is it uses 4N-2 clock states for N number of inputs that is for the design of SDN and number of clock cycles required for the combinational circuit depends upon the number of stages. The design of 2 to 4 line decoder,4*1 Multiplexer 1*4 demultiplexer for QCA . Designed circuits are simulated by using QCA designer V2.0.3 software and calculated the delay of each circuit designed and the area occupied by the designed circuit.