Performance Analysis of Dual Metal Gate Modified Source Fully Depleted SOI MOSFET

Volume 5 Issue 2 May - July 2016

Research Paper

Performance Analysis of Dual Metal Gate Modified Source Fully Depleted SOI MOSFET

Sandeep Tripathi* , VimalKumar Mishra**, R. K. Chauhan***

* PG Scholar, Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh, India.

** Research Scholar, Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology Gorakhpur, Uttar Pradesh, India.

*** Professor, Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh, India.

Tripathi,S., Mishra,V,K., and Chauhan.R.K. (2016). Performance Analysis of Dual Metal Gate Modified Source Fully Depleted SOI MOSFET. i-manager's Journal on Embedded Systems, 5(2), 7-12. https://doi.org/10.26634/jes.5.2.11384

Abstract

This paper presents a performance analysis of the novel features offered by Dual- Metal Gate (DMG) Modified Source Fully Depleted Silicon-On-Insulator (MS FD SOI) MOSFET. The problem that arises in the use of polysilicon (poly-Si) gate material is that the depletion region below the gate increases causing higher gate resistance. Dual-metal gate technology is one approach that employs a Dual Metal Gate (DMG) with suitable mid-gap work function to alleviate the above mentioned issue. The electrical performance of DMG MS FD SOI MOSFET has been compared with the single gate MS FD SOI MOSFET. The DMG structure shows high immunity towards suppression of short channel effects and it has been found that the device is also showing low off-state leakage current, low subthreshold slope, and high drive current. Moreover, the device is optimized using work function engineering at different gate metals. The structure of DMG has been simulated and analyzed using ATLAS device simulator.