A Parallel Multiplier - Accumulator Based On Radix - 2 Modified Booth Algorithm By Using Spurious Power Suppression Tecnique

Vol. 2 No.1

Year: 2013

 
Issue: Feb-Apr

Title : A Parallel Multiplier - Accumulator Based On Radix - 2 Modified Booth Algorithm By Using Spurious Power Suppression Tecnique  

Author Name : S.Tabasum, M.P.Chennaiah 

Synopsis : 

In this paper, the authors proposed a new architecture of Multiplier-And-Accumulator (MAC) for high-speed arithmetic. This can be implement by using radix-2 booth encoder .By combining multiplication with accumulation and devising a hybrid type of Carry Save Adder (CSA), the performance was improved. This includes the design exploration and applications of a Spurious-Power Suppression Technique (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs. Power dissipation is recognized as a critical parameter in modern VLSI field. In Very Large Scale Integration(VLSI), Low power VLSI design is necessary to meet MOORE'S law and to produce consumer electronics with more back up and less processing systems. The proposed MAC accumulates the intermediate results in the type of sum and carry bits instead of the output of the final adder, which made it possible to optimize the pipeline scheme to improve the performance. The objective of a good multiplier is to provide a physically compact, good speed and low power consuming chip. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power that is the major part of power dissipation.