VLSI Based Low Power Hardware Design Using Distributed Arithmetic (DA) Centered 2d Adam7 Transform For The Proposed Image Compression Algorithm

Vol. 2 No.2

Year: 2013

Issue: May-Jul

Title : VLSI Based Low Power Hardware Design Using Distributed Arithmetic (DA) Centered 2d Adam7 Transform For The Proposed Image Compression Algorithm

Author Name : L. Vigneash, C. N. Marimuthu , J. Joseph Lynn

Synopsis :

The need for an efficient technique for compression of images is ever increasing because, the raw images need large amounts of disk space where seem to be a big disadvantage during transmission and storage. Even though, there are so many compression techniques already present, a better technique which is faster, memory efficient and simple, surely suits the requirements of the user. We have planned to design the hardware design flow of Distributed Arithmetic (DA) based 2-D Adam7 algorithm for the proposed image compression algorithm. Accordingly to, an effective 2-D Adam7 algorithm will be performed on input image using well-known Distributed Arithmetic (DA) technique, which exploits the LUT-based FPGA structure to build multiplier-less filter bank, the main component in a Adam7 structure. After computing the Adam7 algorithm, the suitable Adam7 co-efficient is selected and then, applied DPCM (Differential Pulse-Code Modulation) that is a transformation for increasing the compressibility of an image. Finally, the transformed image is given to Huffman-encoder that is designed by merging the lowest probable symbols in such a way that, the images will get compressed. For implementation, the DA-based Adam7 Algorithm is modeled in Simulink and tested. The Verilog source code is developed for the algorithm. All the modules are simulated in Xilinx tool and the final design is verified with Verilog test benches. The final design is implemented in Xilinx Atlys Spartan 6 FPGA Kit.