A Parallel Multiplier - Accumulator Based On Radix - 2 Modified Booth Algorithm By Using Spurious Power Suppression Tecnique

Vol. 2 No.1

Year: 2013

 
Issue: Feb-Apr

Title : A Parallel Multiplier - Accumulator Based On Radix - 2 Modified Booth Algorithm By Using Spurious Power Suppression Tecnique  

Author Name : S.Tabasum, M.P.Chennaiah 

Synopsis : 

In this paper, the authors proposed a new architecture of Multiplier-And-Accumulator (MAC) for high-speed arithmetic. This can be implement by using radix-2 booth encoder .By combining multiplication with accumulation and devising a hybrid type of Carry Save Adder (CSA), the performance was improved. This includes the design exploration and applications of a Spurious-Power Suppression Technique (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs. Power dissipation is recognized as a critical parameter in modern VLSI field. In Very Large Scale Integration(VLSI), Low power VLSI design is necessary to meet MOORE'S law and to produce consumer electronics with more back up and less processing systems. The proposed MAC accumulates the intermediate results in the type of sum and carry bits instead of the output of the final adder, which made it possible to optimize the pipeline scheme to improve the performance. The objective of a good multiplier is to provide a physically compact, good speed and low power consuming chip. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power that is the major part of power dissipation.  

Design of High speed Modified Booth Encoded Parallel Multiplier

Vol. 2 No.1

Year: 2013

 
Issue: Feb-Apr

Title : Design of High speed Modified Booth Encoded Parallel Multiplier

   

Author Name : C.Padma, yarraballi mahesh

   

Synopsis :

  

This paper presents the design and implementation of signed-unsigned Modified Booth Encoding multiplier. Thus, the requirement of the modern computer system is a dedicated and very high speed multiplier unit that can perform multiplication operation on signed as well as unsigned numbers. The conventional Modified Booth Encoding (MBE) generates an irregular partial product array because of the extra partial product bit at the least significant bit position of each partial product row. The modified Booth Encoder circuit generates half the partial products in parallel. By extending sign bit of the operands and generating an additional partial product. The Carry Save Adder (CSA) tree and the final Carry Look Ahead (CLA) adder used to speed up the multiplier operation. The resultant multiplier shows best performance than others. Since the proposed multiplier operates at GHz ranges.  

Microcontroller based Under/Over Voltage and Double Phasing Fault Protection System: Design and Simulation

Vol. 2 No.1

Year: 2013

 
Issue: Feb-Apr

Title : Microcontroller based Under/Over Voltage and Double Phasing Fault Protection System: Design and Simulation

Author Name : M. Rizwan Khan, Basharat Ahmad

Synopsis :

A microcontroller based system is designed and developed to protect the house hold electrical appliances, from double phasing fault and fluctuation of line voltages. This device is tested with upper and lower cutoff voltages set at 150V rms as lower Limit and 250V rms as Upper Limit for the desired voltage range. The system is simulated and tested on Matlab R2010b and then implemented. The ATMega16 Microcontroller from ATMEL is used to implement the system. The Hex file for the microcontroller is developed using Code Vision CVAVR Programming pad and compiler.

Fault Analysis on Grid Connected MPPT Based Photovoltaic System

Vol. 2 No.1

Year: 2013

 
Issue: Feb-Apr

Title : Fault Analysis on Grid Connected MPPT Based Photovoltaic System 

Author Name : Sibasish Panda, Dr Anup Kumar Panda , Dr H.N Pratihari 

Synopsis :

This paper presents the simulation model of a 3.5 kW PV array followed by a boost converter, which boost up the output voltage of the PV array. Maximum Power Point Tracking (MPPT) can effectively improve the solar energy conversion efficiency of PV array, in this paper Perturb- and – Observe (P&O) algorithm has been used to achieve this function. Grid connected PV system needs a three phase inverter for synchronization. The inverter control system modeling has been carried out in Matlab/Simulink 2010 environment with the aids of the proportional-integral controllers, sinusoidal vectored pulse width modulation technique and park transformation. Phase Locked Loop (PLL) is used to lock the grid frequency and phase. Finally different types of AC faults are created on the grid side and Total Harmonic Distortion (THD) is calculated in each of the case.

Clock Pair Shared Pulsed Flipflop

Vol. 2 No.1

Year: 2013

 
Issue: Feb-Apr

Title : Clock Pair Shared Pulsed Flipflop

Author Name : P. Hemanth Kumar, G Rajesh

Synopsis: 

Low power flip-flops which play a vital role for the design of low-power digital systems. Flip flops and latches consume large amount of power due to redundant transitions and clocking system. In addition, the energy consumed by low skew clock distribution network is steadily increasing and becoming a larger fraction of the chip power. Almost, 30% -60% of total power dissipation in a system is due to flip flops and clock distribution network. In order to achieve a design that is both high performances while also being power efficient, careful attention must be paid to the design of flip flops and latches. The authors survey a set of flip flops designed for low power and High performance.